The present invention relates to a method of fabricating a semiconductor integrated circuit device (hereinafter called a semiconductor IC device); and, more particularly, the invention relates to a technique that can be effectively applied to a photolithography process (hereinafter, simply referred to as lithography) for the transfer of a predetermined pattern to a semiconductor wafer (hereinafter, simply referred to as wafer) using a photomask (hereinafter, simply referred to as mask) in the manufacture of a semiconductor IC device.
In the manufacture of a semiconductor IC device, a lithography technique is used as a method of transferring a fine pattern to a wafer. In the lithography technique, a projection aligner is mainly used to form a device pattern by transferring the pattern of a mask mounted on the projection aligner onto a wafer. This lithography technique is described, for example, in Japanese Unexamined Patent Publication No. 135402/1999. Namely, this reference discloses a technique for allocating an auxiliary aperture to such a degree as to not be resolved in the periphery of a main aperture provided to form a contact hole of a memory device in the mask and for utilizing a modified lighting or the like for the exposing process.
However, the inventors of the present invention have found that the above-referenced lithography technique has the following inherent problems. Namely, with improvement in the scale-down, the margin for depth of focus decreases, and, thereby, the resolution of the patterns is lowered. Moreover, when a coarse region wherein patterns are discretely allocated on the same layer and a fine region wherein patterns are closely allocated coexist, a difference is generated in the pattern sizes of such coarse region and fine region. Moreover, the size accuracy of patterns existing at the boundary between the coarse region and fine region is deteriorated.